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K4M283233H - F(H)N/G/L/F
1M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA FEATURES
* 3.0V & 3.3V power supply. * LVCMOS compatible with multiplexed address. * Four banks operation. * MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). * EMRS cycle with address key programs. * All inputs are sampled at the positive going edge of the system clock. * Burst read single-bit write operation. * Special Function Support. -. PASR (Partial Array Self Refresh). -. Internal TCSR (Temperature Compensated Self Refresh) -. DS (Driver Strength) * DQM for masking. * Auto refresh. * * * * 64ms refresh period (4K cycle). Commercial Temperature Operation (-25C ~ 70C). Extended Temperature Operation (-25C ~ 85C). 90Balls FBGA ( -FXXX -Pb, -HXXX -Pb Free).
Mobile SDRAM
GENERAL DESCRIPTION
The K4M283233H is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications.
ORDERING INFORMATION
Part No. K4M283233H-F(H)N/G/L/F60 K4M283233H-F(H)N/G/L/F75 K4M283233H-F(H)N/G/L/F7L Max Freq. 166MHz(CL=3) 133MHz(CL=3), 111MHz(CL=2) 133MHz(CL=3)*1, 83MHz(CL=2) LVCMOS 90 FBGA Pb (Pb Free) Interface Package
- F(H)N/G : Low Power, Extended Temperature(-25C ~ 85C) - F(H)L/F : Low Power, Commercial Temperature(-25C ~ 70C)
Notes : 1. In case of 40MHz Frequency, CL1 can be supported.
Address configuration
Organization 4M x 32 Bank BA0, BA1 Row A0 - A11 Column Address A0 - A7
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.
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K4M283233H - F(H)N/G/L/F
FUNCTIONAL BLOCK DIAGRAM
Mobile SDRAM
I/O Control
LWE
Data Input Register Bank Select
LDQM
1M x 32 Sense AMP 1M x 32 1M x 32 1M x 32
Refresh Counter
Output Buffer
Row Decoder
Row Buffer
DQi
Address Register LRAS CLK CKE
CLK ADD
Column Decoder Col. Buffer
LRAS
LCBR
Latency & Burst Length
LCKE LCBR LWE LCAS
Programming Register LWCBR LDQM
Timing Register CS RAS CAS WE DQM
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K4M283233H - F(H)N/G/L/F
Package Dimension and Pin Configuration
< Bottom View*1 >
E1 9 A B C D E F G D1 H J K L M N P R E Pin Name CLK CS A A1 b CKE A0 ~ A11 D e 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R 1 DQ26 DQ28 VSSQ VSSQ VDDQ VSS A4 A7 CLK DQM1 VDDQ VSSQ VSSQ DQ11 DQ13 2 DQ24 VDDQ DQ27 DQ29 DQ31 DQM3 A5 A8 CKE NC DQ8 DQ10 DQ12 VDDQ DQ15
Mobile SDRAM
< Top View*2 >
90Ball(6x15) FBGA 3 VSS VSSQ DQ25 DQ30 NC A3 A6 NC A9 NC VSS DQ9 DQ14 VSSQ VSS 7 VDD VDDQ DQ22 DQ17 NC A2 A10 NC BA0 CAS VDD DQ6 DQ1 VDDQ VDD 8 DQ23 VSSQ DQ20 DQ18 DQ16 DQM2 A0 BA1 CS WE DQ7 DQ5 DQ3 VSSQ DQ0 9 DQ21 DQ19 VDDQ VDDQ VSSQ VDD A1 A11 RAS DQM0 VSSQ VDDQ VDDQ DQ4 DQ2
Pin Function System Clock Chip Select Clock Enable Address Bank Select Address Row Address Strobe Column Address Strobe Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground [Unit:mm]
z
BA0 ~ BA1 RAS CAS WE DQM0 ~ DQM3 DQ0 ~ 31
< Top View*2 >
#A1 Ball Origin Indicator
SAMSUNG Week
3
K4M283233H-XXXX
VDD/VSS VDDQ/VSSQ
Symbol A A1 E E1 D D1 e b z
Min 0.25 7.90 12.90 0.45 -
Typ 8.00 6.40 13.00 11.20 0.80 0.50 -
Max 1.00 8.10 13.10 0.55 0.10
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K4M283233H - F(H)N/G/L/F
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1.0 50
Mobile SDRAM
Unit V V C W mA
NOTES: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25C ~ 85C for Extended, -25C ~ 70C for Commercial) Parameter Supply voltage VDDQ Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current VIH VIL VOH VOL ILI 2.7 2.2 -0.3 2.4 -2 3.0 3.0 0 3.6 VDDQ + 0.3 0.5 0.4 2 V V V V V uA 1 2 3 IOH = -2mA IOL = 2mA 4 Symbol VDD Min 2.7 Typ 3.0 Max 3.6 Unit V Note 1
NOTES : 1. Under all conditions, VDDQ must be less than or equal to VDD. 2. VIH (max) = 5.3V AC.The overshoot voltage duration is 3ns. 3. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 4. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs. 5. Dout is disabled, 0V VOUT VDDQ.
CAPACITANCE (VDD = 3.0V & 3.3V, TA = 23C, f = 1MHz, VREF =0.9V 50 mV)
Pin Clock RAS, CAS, WE, CS, CKE, DQM Address DQ0 ~ DQ31 Symbol CCLK CIN CADD COUT Min 1.5 1.5 1.5 2.0 Max 3.5 3.0 3.0 4.5 Unit pF pF pF pF Note
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K4M283233H - F(H)N/G/L/F
DC CHARACTERISTICS
Mobile SDRAM
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85C for Extended, -25 to 70C for Commercial) Version Parameter Symbol Test Condition -60 Operating Current (One Bank Active) Precharge Standby Current in power-down mode Burst length = 1 tRC tRC(min) IO = 0 mA CKE VIL(max), tCC = 10ns -75 -7L Unit Note
ICC1
80
65
65
mA
1
ICC2P
0.5 mA 0.5 12 mA 5 5 mA 2 25 mA
ICC2PS CKE & CLK VIL(max), tCC = ICC2N CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns
Precharge Standby Current in non power-down mode
CKE VIH(min), CLK VIL(max), tCC = ICC2NS Input signals are stable ICC3P CKE VIL(max), tCC = 10ns
Active Standby Current in power-down mode
ICC3PS CKE & CLK VIL(max), tCC = ICC3N CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IO = 0 mA Page burst 4Banks Activated tCCD = 2CLKs tRC tRC(min) -N/L Internal TCSR 45 *4 200 150 130
Active Standby Current in non power-down mode (One Bank Active)
ICC3NS
15
mA
Operating Current (Burst Mode)
ICC4
100
75
65
mA
1
Refresh Current
ICC5
140
130 330
120
mA uA
2
85/70 330 230 190
C
3
Self Refresh Current
ICC6
CKE 0.2V -G/F
Full Array 1/2 of Full Array 1/4 of Full Array
uA
NOTES: 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Internal TCSR can be supported. In comercial Temp : 45C/Max 70C. In extended Temp : 45C/Max 85C. 4. It has +/-5 C tolerance. 5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).
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K4M283233H - F(H)N/G/L/F
Mobile SDRAM
AC OPERATING TEST CONDITIONS(VDD = 2.7V 3.6V, TA = -25 ~ 85C for Extended, -25 ~ 70C for Commercial)
Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value 2.4 / 0.4 0.5 x VDDQ tr/tf = 1/1 0.5 x VDDQ See Figure 2 Unit V V ns V
VDDQ
1200 Output VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA 870 30pF Output Z0=50
Vtt=0.5 x VDDQ
50
30pF
Figure 1. DC Output Load Circuit
Figure 2. AC Output Load Circuit
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K4M283233H - F(H)N/G/L/F
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) Version Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time tRAS(max) Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data Number of valid output data Number of valid output data tRC(min) tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3 CAS latency=2 CAS latency=1 60 100 63 2 tRDL + tRP 1 1 1 2 1 0 67.5 Symbol -60 tRRD(min) tRCD(min) tRP(min) tRAS(min) 12 18 18 42 -75 15 18 18 45 -7L 15 22.5 22.5 45
Mobile SDRAM
Unit ns ns ns ns us ns CLK CLK CLK CLK
Note 1 1 1 1
1 2 3 2 2 4
ea
5
NOTES: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. Minimum tRDL=2CLK and tDAL(= tRDL + tRP) is required to complete both of last data write command(tRDL) and precharge command(tRP). 4. All parts allow every cycle column address change. 5. In case of row precharge interrupt, auto precharge and read burst stop. 6. Maximum burst refresh cycle : 8
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K4M283233H - F(H)N/G/L/F
AC CHARACTERISTICS(AC operating conditions unless otherwise noted)
- 60 Parameter CLK cycle time CLK cycle time CLK cycle time CLK to valid output delay CLK to valid output delay CLK to valid output delay Output data hold time Output data hold time Output data hold time CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CAS latency=3 CLK to output in Hi-Z CAS latency=2 CAS latency=1 tSHZ CAS latency=3 CAS latency=2 CAS latency=1 CAS latency=3 CAS latency=2 CAS latency=1 CAS latency=3 CAS latency=2 CAS latency=1 Symbol Min tCC tCC tCC tSAC tSAC tSAC tOH tOH tOH tCH tCL tSS tSH tSLZ 2.5 2.5 2.5 2.0 1.0 1 5.4 6.0 5.4 2.5 2.5 2.5 2.5 2.0 1.0 1 5.4 7 1000 Max Min 7.5 9 5.4 7 1000 Max - 75
Mobile SDRAM
-7L Unit Min 7.5 12 25 5.4 8 20 2.5 2.5 2.5 2.5 2.5 2.0 1.0 1 5.4 8 20 ns ns ns ns ns ns 3 3 3 3 2 ns 2 ns 1,2 1000 ns 1 Max Note
NOTES : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.
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K4M283233H - F(H)N/G/L/F
SIMPLIFIED TRUTH TABLE
COMMAND Register Mode Register Set Auto Refresh H Entry Refresh Self Refresh Exit L H H L L H H Bank Active & Row Addr. Read & Auto Precharge Disable Column Address Auto Precharge Enable Write & Auto Precharge Disable Column Address Auto Precharge Enable Burst Stop Bank Selection Precharge All Banks H Clock Suspend or Active Power Down Entry Exit Entry Precharge Power Down Mode Exit DQM No Operation Command L H H H X L H H H H L V X X X X X V V V H L H L L H L L H H X H X H X X X H V X X V X X V X X X X X X X X H X L L H L X X X X L L X L H X H L X H H X X V V H H H X CKEn-1 CKEn H X H L L L H X CS L RAS L CAS L WE L
Mobile SDRAM
A11, A9 ~ A0
DQM BA0,1 A10/AP X
Note 1, 2 3
OP CODE X
3 3 X 3 Row Address L H L Column Address (A0~A7) Column Address (A0~A7) X V L X H 4 4, 5 4 4, 5 6
H H
X X
L L
H H
L H
L L
X X
V
H
X
X
X X
7
(V=Valid, X=Dont Care, H=Logic High, L=Logic Low) NOTES : 1. OP Code : Operand Code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are the same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. Partial self refresh can be issued only after setting partial self refresh mode of EMRS. 4. BA0 ~ BA1 : Bank select addresses. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency is 0), but in read operation, it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2).
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K4M283233H - F(H)N/G/L/F
A. MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with Normal MRS Address Function BA0 ~ BA1 "0" Setting for Normal MRS A11 ~ A10/AP RFU A9*2 W.B.L A8 A7 A6 A5 A4
Mobile SDRAM
A3 BT
A2
A1 Burst Length
A0
Test Mode
CAS Latency
Normal MRS Mode
Test Mode A8 0 0 1 1 A7 0 1 0 1 Type Mode Register Set Reserved Reserved Reserved A6 0 0 0 0 1 1 1 1 CAS Latency A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Latency Reserved 1 2 3 Reserved Reserved 0 0 1 Burst Single Bit Reserved Reserved 0 Setting for Normal MRS A3 0 1 Burst Type Type Sequential Interleave Mode Select BA1 BA0 Mode A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 Burst Length A0 0 1 0 1 0 1 0 1 BT=0 1 2 4 8 Reserved Reserved Reserved Full Page BT=1 1 2 4 8 Reserved Reserved Reserved Reserved
Write Burst Length A9 Length
Register Programmed with Extended MRS Address Function BA1 BA0 A11 ~ A10/AP A9 RFU*1 A8 A7 A6 DS A5 A4 A3 A2 A1 PASR A0
Mode Select
RFU*1
EMRS for PASR(Partial Array Self Ref.) & DS(Driver Strength)
Mode Select BA1 0 0 1 1 BA0 0 1 0 1 Mode Normal MRS Reserved EMRS for Mobile SDRAM Reserved Reserved Address A11~A10/AP 0 A9 0 A8 0 A7 0 A4 0 A3 0 1
NOTES: 1. RFU(Reserved for future use) should stay "0" during MRS cycle. 2. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.
Driver Strength A6 0 0 1 1 A5 0 1 0 1 Driver Strength Full 1/2 Reserved Reserved A2 0 0 0 0 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1
PASR Size of Refreshed Array Full Array 1/2 of Full Array 1/4 of Full Array Reserved Reserved Reserved Reserved Reserved
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K4M283233H - F(H)N/G/L/F
Partial Array Self Refresh
Mobile SDRAM
1. In order to save power consumption, Mobile SDRAM has PASR option. 2. Mobile SDRAM supports 3 kinds of PASR in self refresh mode : full array, 1/2 of full array, 1/4 of full array.
BA1=0 BA0=0
BA1=0 BA0=1
BA1=0 BA0=0
BA1=0 BA0=1
BA1=0 BA0=0
BA1=0 BA0=1
BA1=1 BA0=0
BA1=1 BA0=1
BA1=1 BA0=0
BA1=1 BA0=1
BA1=1 BA0=0
BA1=1 BA0=1
- Full Array
- 1/2 Array
- 1/4 Array
Partial Self Refresh Area
Internal Temperature Compensated Self Refresh (TCSR)
Note : 1. In order to save power consumption, Mobile-DRAM includes the internal temperature sensor and control units to control the self refresh cycle automatically according to the two temperature range : 45 C and 85 C(for Extended), 70 C(for Commercial). 2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored. 3. It has +/-5 C tolerance. Self Refresh Current (Icc6) Temperature Range -N/L Full Array 85/70 C *3 45 C 330 330 200 150 130 1/2 of Full Array 230 1/4 of Full Array 190 uA -G/F Unit
B. POWER UP SEQUENCE
1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined. - Apply VDD before or at the same time as VDDQ. 2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 3. Issue precharge commands for all banks of the devices. 4. Issue 2 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. 6. Issue a extended mode register set command to define DS or PASR operating type of the device after normal MRS.
For operating with DS or PASR , set DS or PASR mode in EMRS setting stage. In order to adjust another mode in the state of DS or PASR mode, additional EMRS set is required but power up sequence is not needed again at this time. In that case, all banks have to be in idle state prior to adjusting EMRS set.
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K4M283233H - F(H)N/G/L/F
C. BURST SEQUENCE 1. BURST LENGTH = 4
Initial Address Sequential A1 0 0 1 1 A0 0 1 0 1 0 1 2 3 1 2 3 0 2 3 0 1 3 0 1 2 0 1 2 3 1 0 3 2
Mobile SDRAM
Interleave 2 3 0 1 3 2 1 0
2. BURST LENGTH = 8
Initial Address Sequential A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0 Interleave
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